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Features
* Incorporates the ARM7TDMITM ARM(R) Thumb(R) Processor Core
- High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Little-endian - Embedded ICE (In-circuit Emulation) 8-, 16- and 32-bit Read and Write Support 256K Bytes of On-chip SRAM - 32-bit Data Bus - Single-clock Cycle Access Fully Programmable External Bus Interface (EBI) - Maximum External Address Space of 64M Bytes - Up to Eight Chip Selects - Software Programmable 8/16-bit External Data Bus Eight-level Priority, Individually Maskable, Vectored Interrupt Controller - Four External Interrupts, including a High-priority, Low-latency Interrupt Request 32 Programmable I/O Lines Three-channel 16-bit Timer/Counter - Three External Clock Inputs - Two Multi-purpose I/O Pins per Channel Two USARTs - Two Dedicated Peripheral Data Controller (PDC) Channels per USART Programmable Watchdog Timer Advanced Power-saving Features - CPU and Peripheral Can be Deactivated Individually Fully Static Operation: - 0 Hz to 70 MHz Internal Frequency Range at VDDCORE = 1.65V, 85C 2.7V to 3.6V I/O Operating Range 1.65V to 1.95V Core Operating Range -40C to +85C Temperature Range Available in 100-lead TQFP Package
* * *
* * * * * * * * * * *
AT91 ARM(R) Thumb(R) Microcontrollers AT91R40008 Summary
Description
The AT91R40008 microcontroller is a member of the Atmel AT91 16/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high-performance, 32-bit RISC architecture with a high-density, 16-bit instruction set and very low power consumption. Furthermore, it features 256K bytes of on-chip SRAM and a large number of internally banked registers, resulting in very fast exception handling, and making the device ideal for real-time control applications. The AT91R40008 microcontroller features a direct connection to off-chip memory, including Flash, through the fully programmable External Bus Interface (EBI). An 8level priority vectored interrupt controller, in conjunction with the Peripheral Data Controller, significantly improves the real-time performance of the device. The device is manufactured using Atmel's high-density CMOS technology. By combining the ARM7TDMI processor core with a large, on-chip, high-speed SRAM and a wide range of peripheral functions on a monolithic chip, the AT91R40008 is a powerful microcontroller that offers a flexible and high-performance solution to many computeintensive embedded control applications.
Rev. 1732CS-ATARM-02/02
Note: This is a summary document. A complete document is available on our web site at www.atmel.com.
1
Pin Configuration
Figure 1. AT91R40008 in 100-lead TQFP Package
P21/TXD1/NTRI VDDCORE
P15/RXD0
P20/SCK1
P13/SCK0
P14/TXD0
P6/TCLK2
P3/TCLK1
P8/TIOB2
P7/TIOA2
P11/IRQ2
P10/IRQ1
P12/FIQ
P5/TIOB1
P9/IRQ0
P4/TIOA1
P18
75
74
73
P19
72
71
P17
70
69
68
67
66
65
GND
P16
64
63
62
61
60
59
58
57
56
55
54
53
GND
52
P22/RXD1 NWR1/NUB GND NRST NWDOVF VDDIO MCKI P23 P24/BMS P25/MCKO GND GND TMS TDI TDO TCK NRD/NOE NWR0/NWE VDDCORE VDDIO NWAIT NCS0 NCS1 P26/NCS2 P27/NCS3
51
P2/TIOB0
VDDIO
GND
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
P1/TIOA0 P0/TCLK0 D15 D14 D13 D12 VDDIO D11 D10 D9 D8 D7 D6 D5 GND D4 D3 D2 D1 D0 P31/A23/CS4 P30/A22/CS5 VDDIO VDDCORE P29/A21/CS6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 A19
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AT91R40008
1732CS-ATARM-02/02
P28/A20/CS7
A16
GND
A14
A0/NLB
GND
VDDIO
GND
A11
A12
A10
A13
A15
A17
A18
A5
A6
A1
A2
A3
A4
A7
A8
A9
25
1
2
3
4
5
6
7
8
9
AT91R40008
Pin Description
Table 1. AT91R40008 Pin Description
Module Name A0 - A23 D0 - D15 NCS0 - NCS3 CS4 - CS7 NWR0 NWR1 EBI NRD NWE NOE NUB NLB NWAIT BMS FIQ AIC IRQ0 - IRQ2 TCLK0 - TCLK2 TC TIOA0 - TIOA2 TIOB0 - TIOB2 SCK0 - SCK1 USART TXD0 - TXD1 RXD0 - RXD1 PIO WD Clock MCKO NRST Reset NTRI TMS TDI ICE TDO TCK VDDIO Power VDDCORE GND Test Data Output Test Clock I/O Power Core Power Ground Output Input Power Power Ground - - - - - Schmidt trigger, internal pull-up 3V nominal supply 1.8V nominal supply Tri-state Mode Select Test Mode Select Test Data Input Input Input Input Low - - Sampled during reset Schmidt trigger, internal pull-up Schmidt trigger, internal pull-up Master Clock Output Hardware Reset Input Output Input - Low Schmidt trigger P0 - P31 NWDOVF MCKI External Interrupt Request Timer External Clock Multipurpose Timer I/O pin A Multipurpose Timer I/O pin B External Serial Clock Transmit Data Output Receive Data Input Parallel IO line Watchdog Overflow Master Clock Input Input Input I/O I/O I/O Output Input I/O Output Input - - - - - - - - Low - Open-drain Schmidt trigger PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset Function Address Bus Data Bus Chip Select Chip Select Lower Byte 0 Write Signal Upper Byte 1 Write Signal Read Signal Write Enable Output Enable Upper Byte Select Lower Byte Select Wait Input Boot Mode Select Fast Interrupt Request Type Output I/O Output Output Output Output Output Output Output Output Output Input Input Input Active Level - - Low High Low Low Low Low Low Low Low Low - - Sampled during reset PIO-controlled after reset A23 - A20 after reset Used in Byte Write option Used in Byte Write option Used in Byte Write option Used in Byte Select option Used in Byte Select option Used in Byte Select option Used in Byte Select option Comments All valid after reset
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1732CS-ATARM-02/02
Block Diagram
Figure 2. AT91R40008
TMS TDO TDI TCK
Embedded ICE
Reset
NRST
D0-D15
ARM7TDMI Core
ASB
MCKI Clock P25/MCKO 256K Bytes RAM
EBI: External Bus Interface
A1-A19 A0/NLB NRD/NOE NWR0/NWE NWR1/NUB NWAIT NCS0 NCS1 P26/NCS2 P27/NCS3 P28/A20/CS7 P29/A21/CS6 P30/A22/CS5 P31/A23/CS4
ASB Controller AMBA Bridge P12/FIQ P9/IRQ0 P10/IRQ1 P11/IRQ2 P I O AIC: Advanced Interrupt Controller
EBI User Interface
P13/SCK0 P14/TXD0 P15/RXD0 P20/SCK1 P21/TXD1/NTRI P22/RXD1
USART0
2 PDC Channels APB 2 PDC Channels
TC: Timer Counter TC0
P I O
P0/TCLK0 P3/TCLK1 P6/TCLK2 P1/TIOA0 P2/TIOB0 P4/TIOA1 P5/TIOB1 P7/TIOA2 P8/TIOB2
USART1
TC1 TC2
PS: Power Saving P16 P17 P18 P19 P23 P24/BMS WD: Watchdog Timer NWDOVF
Chip ID
PIO: Parallel I/O Controller
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AT91R40008
Architectural Overview
The AT91R40008 microcontroller integrates an ARM7TDMI with embedded ICE interface, memories and peripherals. The architecture consists of two main buses: the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). Designed for maximum performance and controlled by the memory controller, the ASB interfaces the ARM7TDMI processor with the on-chip 32-bit memories, the External Bus Interface (EBI) and the AMBA TM Bridge. The AMBA Bridge drives the APB, which is designed for accesses to on-chip peripherals and optimized for low power consumption. The AT91R40008 microcontroller implements the ICE port of the ARM7TDMI processor on dedicated pins, offering a complete, low-cost and easy-to-use debug solution for target debugging.
Memories
The AT91R40008 microcontroller embeds 256K bytes of internal SRAM. The internal memory is directly connected to the 32-bit data bus and is single-cycle accessible. The AT91R40008 microcontroller features an External Bus Interface (EBI), which enables connection of external memories and application-specific peripherals. The EBI supports 8- or 16-bit devices and can use two 8-bit devices to emulate a single 16-bit device. The EBI implements the early read protocol, enabling faster memory accesses than standard memory interfaces.
Peripherals
The AT91R40008 microcontrollers integrate several peripherals, that are classified as system or user peripherals. All on-chip peripherals are 32-bit accessible by the AMBA Bridge, and can be programmed with a minimum number of instructions. The peripheral register set consists of control, mode, data, status and enable/disable/status registers. An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs and on- and off-chip memories address space without processor intervention. Most importantly, the PDC removes the processor interrupt handling overhead, making it possible to transfer up to 64K contiguous bytes without reprogramming the start address, thus increasing the performance of the microcontroller and reducing the power consumption.
System Peripherals
The External Bus Interface (EBI) controls the external memory or peripheral devices via an 8or 16-bit data bus and is programmed through the Advanced Peripheral Bus (APB). Each chip select line has its own programming register. The Power-saving (PS) module implements the Idle mode (ARM7TDMI core clock stopped until the next interrupt) and enables the user to adapt the power consumption of the microcontroller to application requirements (independent peripheral clock control). The Advanced Interrupt Controller (AIC) controls the internal interrupt sources from the internal peripherals and the four external interrupt lines (including the FIQ) to provide an interrupt and/or fast interrupt request to the ARM7TDMI. It integrates an 8-level priority controller and, using the Auto-vectoring feature, reduces the interrupt latency time. The Parallel Input/Output Controller (PIO) controls up to 32 I/O lines. It enables the user to select specific pins for on-chip peripheral input/output functions and general-purpose input/output signal pins. The PIO controller can be programmed to detect an interrupt on a signal change from each line. The Watchdog (WD) can be used to prevent system lock-up if the software becomes trapped in a deadlock. The Special Function (SF) module integrates the Chip ID, the Reset Status and the Protect registers.
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User Peripherals
Two independently configurable USARTs enable communication at a high baud rate in synchronous or asynchronous mode. The format includes start, stop and parity bits and up to 8 data bits. Each USART also features a Time-out and a Time-guard register, facilitating the use of the two dedicated Peripheral Data Controller (PDC) channels. The 3-channel, 16-bit Timer/Counter (TC) is highly programmable and supports capture or waveform modes. Each TC channel can be programmed to measure or generate different kinds of waves, and can detect and control two input/output signals. The TC also has three external clock signals.
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Associated Documentation
The AT91R40008 is part of the AT91X40 series of microcontrollers, a member of the Atmel AT91 16/32-bit microcontroller family, which is based on the ARM7TDMI processor core. The table below contains details of associated documentation for further reference. Table 2. Associated Documentation
Product Information Internal architecture of processor ARM/Thumb instruction sets Embedded in-circuit-emulator External memory interface mapping Peripheral operations Peripheral user interfaces AT91R40008 DC characteristics Power consumption Thermal and reliability considerations AC characteristics Product overview Ordering information Packaging information Soldering profile Document Title ARM7TDMI (Thumb) Datasheet
AT91x40 Series Datasheet
AT91R40008 Electrical Characteristics
AT91R40008 Summary Datasheet (this document)
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1732CS-ATARM-02/02
Product Overview
Power Supply
The AT91R40008 microcontroller has two types of power supply pins: * * VDDCORE pins, which power the chip core (i.e., the ARM7TDMI, embedded memory and the peripherals). VDDIO pins, which power the I/O lines.
An independent I/O supply allows a flexible adaptation to external component signal levels.
Input/Output Considerations Master Clock
After the reset, the peripheral I/Os are initialized as inputs to provide the user with maximum flexibility. It is recommended that in any application phase, the inputs to the AT91R40008 microcontroller be held at valid logic levels to minimize the power consumption. The AT91R40008 microcontroller has a fully static design and works on the Master Clock (MCK) provided on the MCKI pin from an external source. The Master Clock is also provided as an output of the device on the pin MCKO, which is multiplexed through a general-purpose I/O line. While NRST is active, MCKO remains low. After the reset, the MCKO is valid and outputs an image of the MCK signal. The PIO controller must be programmed to use this pin as standard I/O line.
Reset
Reset restores the default states of the user interface registers (defined in the user interface of each peripheral) and forces the ARM7TDMI to perform the next instruction fetch from address zero. Except for the program counter, the ARM7TDMI registers do not have defined reset states. NRST is active low-level input. It is asserted asynchronously, but exit from reset is synchronized internally to the MCK. The signal presented on MCKI must be active within the specification for a minimum of 10 clock cycles up to the rising edge of NRST to ensure correct operation. The first processor fetch occurs 80 clock cycles after the rising edge of NRST.
NRST Pin
Watchdog Reset
The Watchdog can be programmed to generate an internal reset. In this case, the reset has the same effect as the NRST pin assertion, but the pins BMS and NTRI are not sampled. Boot Mode and Tri-state Mode are not updated. If the NRST pin is asserted and the Watchdog triggers the internal reset, the NRST pin has priority.
Emulation Functions
Tri-state Mode The AT91R40008 microcontroller provides a tri-state mode, which is used for debug purposes. This enables the connection of an emulator probe to an application board without having to desolder the device from the target board. In tri-state mode, all the output pin drivers of the AT91R40008 microcontroller are disabled. To enter tri-state mode, the NTRI pin must be held low during the last 10 clock cycles before the rising edge of NRST. For normal operation, the NTRI pin must be held high during reset by a resistor of up to 400 k. NTRI is multiplexed with I/O line P21 and USART1 serial data transmit line TXD1. Standard RS-232 drivers generally contain internal 400 k pull-up resistors. If TXD1 is connected to a device not including this pull-up, the user must make sure that a high level is tied on NTRI while NRST is asserted.
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AT91R40008
JTAG/ICE Debug ARM standard embedded in-circuit emulation is supported via the JTAG/ICE port. The pins TDI, TDO, TCK and TMS are dedicated to this debug function and can be connected to a host computer via the external ICE interface. In ICE Debug mode, the ARM7TDMI core responds with a non-JTAG chip ID that identifies the microcontroller. This is not fully IEEE1149.1 compliant.
Memory Controller
The ARM7TDMI processor address space is 4G bytes. The memory controller decodes the internal 32-bit address bus and defines three address spaces: * * * Internal memories in the four lowest megabytes Middle space reserved for the external devices (memory or peripherals) controlled by the EBI Internal peripherals in the four highest megabytes
In any of these address spaces, the ARM7TDMI operates in Little-endian mode only. Internal Memories The AT91R40008 microcontroller integrates 256K bytes of internal SRAM. All internal memories are 32 bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) or word (32-bit) accesses are supported and are executed within one cycle. Fetching Thumb or ARM instructions is supported and internal memory can store twice as many Thumb instructions as ARM ones. The SRAM is mapped at address 0x0 (after the Remap command), allowing ARM7TDMI exception vectors between 0x0 and 0x20 to be modified by the software. Placing the SRAM on-chip and using the 32-bit data bus bandwidth maximizes the microcontroller performance and minimizes the system power consumption. The 32-bit bus increases the effectiveness of the use of the ARM instruction set and the ability of processing data that is wider than 16-bit, thus making optimal use of the ARM7TDMI advanced performance. Being able to dynamically update application software in the 256-Kbyte SRAM adds an extra dimension to the AT91R40008. Boot Mode Select The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI executes the instruction stored at this address. This means that this address must be mapped in nonvolatile memory after the reset. The input level on the BMS pin during the last 10 clock cycles before the rising edge of the NRST selects the type of boot memory (see Table 3). The BMS pin is multiplexed with the I/O line P24, which can be programmed after reset like any standard PIO line. Table 3. Boot Mode Select
BMS 1 0 Boot Memory External 8-bit memory on NCS0 External 16-bit memory on NCS0
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1732CS-ATARM-02/02
Remap Command
The ARM vectors (Reset, Abort, Data Abort, Pre-fetch Abort, Undefined Instruction, Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors to be redefined dynamically by the software, the AT91R40008 microcontroller uses a Remap command that enables switching between the boot memory and the internal primary SRAM bank addresses. The Remap command is accessible through the EBI User Interface by writing one in RCB of EBI_RCR (Remap Control Register). Performing a Remap command is mandatory if access to the other external devices (connected to chip-selects 1 to 7) is required. The Remap operation can only be changed back by an internal reset or an NRST assertion. The abort signal providing a Data Abort or a Pre-fetch Abort exception to the ARM7TDMI is asserted when accessing an undefined address in the EBI address space. No abort is generated when reading the internal memory or by accessing the internal peripherals, whether or not the address is defined.
Abort Control
External Bus Interface
The External Bus Interface handles the accesses between addresses 0x0040 0000 and 0xFFC0 0000. It generates the signals that control access to the external devices, and can be configured from eight 1M byte banks up to four 16M bytes banks. It supports byte-, half-wordand word-aligned accesses. For each of these banks, the user can program: * * * Number of wait states Number of data float times (wait time after the access is finished to prevent any bus contention in case the device is too long in releasing the bus) Data bus width (8-bit or 16-bit)
The user can program the EBI to control one 16-bit device (Byte Select Access mode) with a 16-bit wide data bus or two 8-bit devices in parallel that emulate a 16-bit memory (Byte Write Access mode). The External Bus Interface also features the Early Read Protocol, configurable for all the devices, which significantly reduces access time requirements on an external device in the case of single-clock cycle access.
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Peripherals
The AT91R40008 microcontroller peripherals are connected to the 32-bit wide Advanced Peripheral Bus. Peripheral registers are only word accessible - byte and half-word accesses are not supported. If a byte or a half-word access is attempted, the memory controller automatically masks the lowest address bits and generates a word access. Each peripheral has a 16-Kbyte address space allocated (the AIC only has a 4-Kbyte address space). Peripheral Registers The following registers are common to all peripherals: * * * * * Control Register - write-only register that triggers a command when a one is written to the corresponding position at the appropriate address. Writing a zero has no effect. Mode Register - read/write register that defines the configuration of the peripheral. Usually has a value of 0x0 after a reset. Data Registers - read and/or write registers that enable the exchange of data between the processor and the peripheral. Status Register - read-only register that returns the status of the peripheral. Enable/Disable/Status Registers are shadow command registers. Writing a one in the Enable Register sets the corresponding bit in the Status Register. Writing a one in the Disable Register resets the corresponding bit and the result can be read in the Status Register. Writing a bit to zero has no effect. This register access method maximizes the efficiency of bit manipulation and enables modification of a register with a single noninterruptible instruction, replacing the costly read-modify-write operation.
Unused bits in the peripheral registers are shown as "-" and must be written at 0 for upward compatibility. These bits read 0. Peripheral Interrupt Control The Interrupt Control of each peripheral is controlled from the Status Register using the interrupt mask. The Status Register bits are ANDed to their corresponding interrupt mask bits and the result is then ORed to generate the Interrupt Source signal to the Advanced Interrupt Controller. The interrupt mask is read in the Interrupt Mask Register and is modified with the Interrupt Enable Register and the Interrupt Disable Register. The enable/disable/status (or mask) makes it possible to enable or disable peripheral interrupt sources with a non-interruptible single instruction. This eliminates the need for interrupt masking at the AIC or Core level in realtime and multi-tasking systems. Peripheral Data Controller The AT91R40008 microcontroller has a 4-channel PDC dedicated to the two on-chip USARTs. One PDC channel is dedicated to the receiver and one to the transmitter of each USART. The user interface of a PDC channel is integrated in the memory space of each USART. It contains a 32-bit Address Pointer Register (RPR or TPR) in addition to a 16-bit Transfer Counter Register (RCR or TCR). When the programmed number of transfers are performed, a status bit indicating the end of transfer is set in the USART Status Register and an interrupt can be generated.
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System Peripherals
PS: Power-saving The Power-saving feature optimizes power consumption, enabling the software to stop the ARM7TDMI clock (Idle mode), restarting it when the module receives an interrupt (or reset). It also enables on-chip peripheral clocks to be enabled and disabled individually, matching power consumption and application need. The Advanced Interrupt Controller has an 8-level priority, individually maskable, vectored interrupt controller, and drives the NIRQ and NFIQ pins of the ARM7TDMI from: * * * The external fast interrupt line (FIQ) The three external interrupt request lines (IRQ0 - IRQ2) The interrupt signals from the on-chip peripherals
AIC: Advanced Interrupt Controller
The AIC is extensively programmable offering maximum flexibility, and its vectoring features reduce the real-time overhead in handling interrupts. The AIC also features a spurious vector, which reduces spurious interrupt handling to a minimum, and a protect mode that facilitates the debug capabilities. PIO: Parallel I/O Controller The AT91R40008 microcontroller has 32 programmable I/O lines. Six pins are dedicated as general-purpose I/O pins. Other I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins. The PIO controller enables generation of an interrupt on input change on any of the PIO pins. The Watchdog is built around a 16-bit counter and is used to prevent system lock-up if the software becomes trapped in a deadlock. It can generate an internal reset or interrupt, or assert an active level on the dedicated pin NWDOVF. All programming registers are password-protected to prevent unintentional programming. The AT91R40008 microcontroller provides registers that implement the following special functions: * * * Chip identification RESET status Protect mode
WD: Watchdog
SF: Special Function
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AT91R40008
User Peripherals
USART: Universal Synchronous/ Asynchronous Receiver Transmitter The AT91R40008 microcontroller provides two identical, full-duplex, universal synchronous/asynchronous receiver/transmitters. Each USART has its own baud rate generator and two dedicated Peripheral Data Controller channels. The data format includes a start bit, up to 8 data bits, an optional programmable parity bit and up to 2 stop bits. The USART also features a Receiver Time-out Register, facilitating variable length frame support when it is working with the PDC, and a Time-guard Register, used when interfacing with slow remote equipment. TC: Timer/Counter The AT91R40008 microcontroller features a Timer/Counter block that includes three identical 16-bit Timer/Counter channels. It is possible to independently program each channel to perform a wide range of functions, including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. The Timer/Counter can be used in Capture or Waveform mode, and all three counter channels can be started simultaneously and chained together.
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1732CS-ATARM-02/02
Ordering Information
Table 4. Ordering Information
Ordering Code AT91R40008-66AI Package TQFP 100 Operation Range Industrial (-40C to 85C)
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AT91R40008
Packaging Information
Figure 3. 100-lead Thin Quad Flat Pack Package Outline
aaa
bbb
PIN 1
c
c1 L1
1732CS-ATARM-02/02
S ccc
ddd R1 1 R2 0.25
15
Table 5. Common Dimensions (mm)
Symbol c c1 L L1 R2 R1 S q 0.08 0.08 0.2 0 0 11 11 12 12 13 13 1.6 0.05 1.35 1.4 Tolerances of Form and Position aaa bbb 0.2 0.2 0.15 1.45 3.5 7 Min 0.09 0.09 0.45 0.6 1.00 REF 0.2 Nom Max 0.2 0.16 0.75
1 2 3
A A1 A2
Table 6. Lead Count Dimensions (mm)
Pin Count 100 D/E BSC 16.0 D1/E1 BSC 14.0 b Min 0.17 Nom 0.22 Max 0.27 Min 0.17 b1 Nom 0.2 Max 0.23 e BSC 0.50
ccc 0.10
ddd 0.06
Table 7. Device and 100-lead TQFP Package Maximum Weight
710 mg
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AT91R40008
Soldering Profile
Table 8 gives the recommended soldering profile from J-STD-20. Table 8. Soldering Profile
Convection or IR/Convection Average Ramp-up Rate (183C to Peak) Preheat Temperature 125C 25C Temperature Maintained Above 183C Time within 5C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25C to Peak Temperature 3C/sec. max. 120 sec. max 60 sec. to 150 sec. 10 sec. to 20 sec. 220 +5/-0C or 235 +5/-0C 6C/sec. 6 min. max 60 sec. 215 to 219C or 235 +5/-0C 10C/sec. VPR 10C/sec.
Small packages may be subject to higher temperatures if they are reflowed in boards with larger components. In this case, small packages may have to withstand temperatures of up to 235C, not 220C (IR reflow). Recommended package reflow conditions depend on package thickness and volume. See Table 9. Table 9. Recommended Package Reflow Conditions (1, 2, 3)
Parameter Convection VPR IR/Convection Temperature 235 +5/-0C 235 +5/-0C 235 +5/-0C
When certain small thin packages are used on boards without larger packages, these small packages may be classified at 220C instead of 235C.
Notes: 1. The packages are qualified by Atmel by using IR reflow conditions, not convection or VPR. 2. By default, the package level 1 is qualified at 220C (unless 235C is stipulated). 3. The body temperature is the most important parameter but other profile parameters such as total exposure time to hot temperature or heating rate may also influence component reliability.
A maximum of three reflow passes is allowed per component.
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Document Details
Title Literature Number AT91R40008 Summary 1732S
Revision History
Version A Version B Version C Publication Date: Jun-01 Publication Date: Jul-01 Publication Date: 21-Jan-02
Revisions Since Previous Version Page: 9 Page: 14 Page: 16 Page: 17
Added information to section Internal Memories Change in Table 4 Added Table 6, Package Weight Added section Soldering Profile
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems.
ATMEL (R) is the registered trademark of Atmel. ARM (R), Thumb (R) and ARM Powered (R) are the registered trademarks of ARM Ltd.; ARM7TDMITM is the trademark of ARM Ltd. Other terms and product names may be the trademarks of others. Printed on recycled paper.
1732CS-ATARM-02/02 0M

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